Non-volatile memory in CMOS logic process
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United States of America Patent
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Mar 2, 2010
Grant Date -
May 3, 2007
app pub date -
Oct 28, 2005
filing date -
Oct 28, 2005
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Abstract
A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).
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