Buffer circuit with integrated loss canceling
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United States of America Patent
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Sep 17, 2013
Grant Date -
Dec 30, 2010
app pub date -
Jun 29, 2009
filing date -
Jun 29, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
A filter circuit enhances a deficient Q-value in a filter stage and buffers the filter stage from subsequent filter stages using a common active device. A filter circuit includes a first buffered filtering stage including a first Q-deficient filter stage to receive an input signal and a first Q-enhancement buffer stage. The first Q-enhancement buffer stage is coupled to the first Q-deficient filter stage, wherein the first Q-enhancement buffer stage includes a single active device to increase a Q-value of the first Q-deficient filter stage and isolate the first Q-deficient filter stage from any subsequent filter stage. A filtering method includes filtering an input signal in a first Q-deficient filter stage and enhancing a deficient Q-value of the first Q-deficient filter stage with an active device. The method further includes buffering the first Q-deficient filter stage from any subsequent filter stage with the active device.
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