Processing device with address translation probing and methods
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United States of America Patent
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Mar 17, 2015
Grant Date -
Jun 26, 2014
app pub date -
Dec 21, 2012
filing date -
Dec 21, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued.
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