Semiconductor memory device having memory cells requiring no refresh operations
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United States of America Patent
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Aug 10, 2004
Grant Date -
Oct 2, 2003
app pub date -
Oct 3, 2002
filing date -
Mar 28, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory cell is provided with an N-channel MOS transistor as a transfer gate, a capacitor for accumulating charges corresponding to stored information, and a charge compensating circuit. Charge compensating circuit is a bi-stable circuit formed of two stages of inverters and latches a logic level of a node. Load resistors of inverters are constituted of P-channel thin film transistors made of polycrystalline polysilicon which can be formed on upper layers of N-channel MOS transistors as bulk transistors. As a result, a semiconductor memory device can realize a higher packing density and a larger capacity close to those of a DRAM without requiring refresh operations.
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