High thermal conductivity vias by additive processing
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United States of America Patent
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Jun 13, 2023
Grant Date -
May 31, 2018
app pub date -
Nov 26, 2016
filing date -
Nov 26, 2016
priority date (Note) -
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Abstract
An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.
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