N-bits successive approximation register analog-to-digital converting circuit

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United States of America Patent

PATENT NO 8344931
APP PUB NO 20120306679A1
SERIAL NO

13150508

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Abstract

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The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

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Patent Owner(s)

  • UNIVERSITY OF MACAU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chan, Chi-Hang Macau, CN 5 49
Chio, U-Fat Macau, CN 6 37
Maloberti, Franco Torre d'Isola, IT 37 565
Martins, Rui Paulo Da Silva Macau, CN 32 152
Sin, Sai-Weng Macau, CN 9 59
U, Seng-Pan Macau, CN 14 150
Zhu, Yan Macau, CN 216 1233

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