Instruction block allocation

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United States of America Patent

PATENT NO 11755484
APP PUB NO 20160378661A1
SERIAL NO

14752418

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Abstract

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Apparatus and methods are disclosed for throttling processor operation in block-based processor architectures. In one example of the disclosed technology, a block-based instruction set architecture processor includes a plurality of processing cores configured to fetch and execute a sequence of instruction blocks. Each of the processing cores includes function resources for performing operations specified by the instruction blocks. The processor further includes a core scheduler configured to allocate functional resources for performing the operations. The functional resources are allocated for executing the instruction blocks based, at least in part, on a performance metric. The performance metric can be generated dynamically or statically based on branch prediction accuracy, energy usage tolerance, and other suitable metrics.

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Patent Owner(s)

  • MICROSOFT TECHNOLOGY LICENSING, LLC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Burger, Douglas C Bellevue, US 166 3379
Gray, Jan S Bellevue, US 20 698
Smith, Aaron L Seattle, US 52 970

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