Address layout over physical memory
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United States of America Patent
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Jan 1, 2019
Grant Date -
N/A
app pub date -
Aug 29, 2017
filing date -
Aug 29, 2017
priority date (Note) -
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status (Latency Note)
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Abstract
An address translation device (ATD) can be used to translate a physical address of a memory line to a storage location within a main memory. The main memory can include multiple memory devices, each including at least one memory portion. Each of the memory portions can be contiguous and have a uniform size. The memory line can be stored within one of the memory portions. The ATD can include a data table structure. Consecutive rows of the data table structure can be configured such that each of the rows uniquely identifies one of the memory portions. The ATD can also include an index calculation unit configured to calculate a row index. The row index can be used to identify the row of the data table structure that identifies the memory portion that includes the storage location of the memory line.
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