Semiconductor chip stack with locking through vias
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United States of America Patent
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Dec 5, 2023
Grant Date -
N/A
app pub date -
Jul 23, 2020
filing date -
Jul 23, 2020
priority date (Note) -
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Abstract
Various semiconductor chips and chip stack arrangements are disclosed. In one aspect, a semiconductor chip stack is provided that includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first logic layer and a first semiconductor layer on the first logic layer. The first semiconductor layer has plural first through-silicon transistors operable to selectively control the transmission of data from the first semiconductor chip to the second semiconductor chip and has plural first through-silicon vias to convey control signals to the second semiconductor chip.
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