Method and apparatus for screening bit line of a static random access memory (SRAM) for excessive leakage current
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United States of America Patent
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Sep 7, 2010
Grant Date -
May 7, 2009
app pub date -
Nov 5, 2007
filing date -
Nov 5, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method including: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage; preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage; preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and comparing the voltage of the BLT under the foregoing conditions to a threshold voltage.
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