Memory performance optimization method, memory control circuit unit and memory storage device

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United States of America Patent

PATENT NO 11693567
APP PUB NO 20230127512A1
SERIAL NO

17533020

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Abstract

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A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

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Patent Owner(s)

  • HEFEI CORE STORAGE ELECTRONIC LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cao, Kuai Anhui, CN 5 0
Cheng, Xu Hui Anhui, CN 5 1
Rao, Dong Sheng Hefei, CN 4 0
Wang, Xin Anhui, CN 1347 12675
Zhang, Jing Anhui, CN 847 8312
Zhu, Qi-Ao Anhui, CN 16 26

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