Memory module having an open-drain output for parity error and for training sequences
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United States of America Patent
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Jul 12, 2022
Grant Date -
May 14, 2020
app pub date -
Nov 11, 2019
filing date -
Jun 12, 2009
priority date (Note) -
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Abstract
According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.
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