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Abstract

An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode. A clock calibrator measures the frequency difference between 1/(S)(n) times the frequency of the primary digital transceiver clock signal and the frequency of the secondary digital transceiver clock signal as a function of time. A secondary mode timer indicates the amount of time the secondary mode is in effect. A controller calculates the cumulative resluting frequency error, and produces a signal for advancing or retarding a master timer to reduce the frequency error between the long PN generator and the short PN generator on the one hand, and the CDMA network time on the other hand.

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