High performance, high capacity memory modules and systems
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United States of America Patent
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Dec 6, 2022
Grant Date -
Nov 5, 2020
app pub date -
May 21, 2020
filing date -
Aug 6, 2015
priority date (Note) -
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Abstract
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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