Importance

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Abstract

A pulse signal processing circuit includes a NAND circuit that accepts periodic input pulses and an upper-limit detection signal from an upper limit detector and, when both an input pulse and the upper-limit detection signal are present, provides a setting signal to a flip-flop. When the flip-flop is set, it provides a discharging signal to activate a constant discharging current source. A capacitor is discharged by the discharging current source until the potential across the capacitor reaches a lower reference potential, when a lower-limit detection signal from a lower limit detector resets the flip-flop to terminate the discharging signal. The discharging signal also comprises the output pulse of the processing circuit. Resetting the flip-flop initiates a charging signal to activate a constant charging current source to charge the capacitor until it reaches an upper reference potential, when the upper-limit detection signal is provided to the NAND circuit to condition it to receive the next input pulse. Meanwhile, until the upper-limit detection signal is initiated, noise on the input line cannot provide an output pulse because that noise will not provide the setting signal from the NAND circuit to initiate the discharging signal.

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First Claim