Phase locked loop clock source provided with a plurality of frequency adjustments
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Nov 28, 2000
Grant Date -
N/A
app pub date -
Jan 21, 1999
filing date -
Feb 27, 1997
priority date (Note) -
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Abstract
An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.
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