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Abstract

An equalizing transistor is connected between first and second data lines to which data corresponding to data stored in a memory cell selected by an address is outputted. When the equalizing pulse is applied to the control terminal of the equalizing transistor, the first and second data lines are made conductive with respect to each other so that the data lines are set at a predetermined equal potential. An output buffer switch has first and second output switches connected in series between a power source supply terminal and ground. An interconnection node between the output switches is a data output terminal. One or the other of the pair of data lines are connected to the control nodes of the first and second output switches. A data line switch is connected between the equalizing transistor and the output buffer switch of at least one of the pair of data lines. The data line switch is turned on and off by the equalizing pulse. A latch is connected between the data switch and the correspondingly connected ones of the output switch at said the lines. The latch latches the potentials at the data lines immediately before the turn-off of the data line switch and applies the latched potentials to the control terminals of the output switch.

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