Microprocessor with prediction unit pipeline that provides a next fetch address at a rate of one per clock cycle

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United States of America Patent

PATENT NO 11816489
SERIAL NO

17879318

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Abstract

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A microprocessor includes a prediction unit pipeline having a first stage that makes first predictions at a rate of one per clock cycle. Each first prediction comprises a hash of a fetch address of a current fetch block and branch history update information produced by a previous fetch block immediately preceding the current fetch block. Second one or more stages, following the first stage, with a latency of N (at least one) clock cycles, use the first predictions to make second predictions at a rate of one per clock cycle. Each second prediction includes a fetch address of a next fetch block immediately succeeding the current fetch block and branch history update information produced by the current fetch block. For each second prediction of the second predictions, logic uses the second prediction to check whether the first prediction made N−1 clock cycles earlier than the second prediction is a mis-prediction.

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Patent Owner(s)

Patent OwnerAddress
VENTANA MICRO SYSTEMS INC20863 STEVENS CREEK BLVD SUITE 456 CUPERTINO CA 95014

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Favor, John G San Francisco, US 92 2942
Michael, Michael N Folsom, US 7 0

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