Importance

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Abstract

A stackable voltage comparator circuit that may be used in an analog voltage address decoder circuit for performing voltage window comparisons. The voltage comparator circuit includes a plurality of voltage comparator circuit cells, each of which includes a differential input stage made up of a pair of transistors which receives a current source. A first comparator circuit cell includes a differential input pair of transistors with one of the transistors having a first collector and a second collector, with the second collector being coupled to an output line. The first comparator circuit cell compares an input window with a first threshold voltage and produces an output at the output line. A second comparator circuit cell compares the input voltage with a second threshold voltage and includes a second differential input pair of transistors. The second comparator circuit cell has an input coupled to the output line of the first comparator circuit for receiving current when the input voltage is less than the first threshold voltage and provides an output indicative of whether the input voltage is within a voltage window bounded by the first and second threshold voltages.

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First Claim