REDUCING SHORT CIRCUIT POWER IN CMOS INVERTER CIRCUITS
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United States of America Patent
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-
Feb 3, 2004
Grant Date -
Feb 5, 2004
app pub date -
Jul 31, 2002
filing date -
Jul 31, 2002
priority date (Note) -
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Abstract
A CMOS inverter circuit containing a PMOS transistor, a NMOS transistor, and feedback driver circuits not containing common input inverter circuits. The feedback driver circuits minimize (prevent) an amount of time both the NMOS and PMOS transistors are in an ON state at the same time, thereby reducing short circuit power (i.e., the power dissipated if both the PMOS and NMOS transistors are in an on state). In addition, as the two feedback driver circuits do not contain common input inverter circuits, the short circuit power is further reduced.
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