Testing integrated circuits provided on a carrier
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United States of America Patent
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Jul 4, 1995
Issued Date -
N/A
app pub date -
Oct 10, 1989
filing date -
Sep 10, 1986
priority date (Note) -
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status (Latency Note)
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Abstract
A method for testing integrated circuits provided on a carrier. The circuits include a series input (22) and a series output (24) for test and result patterns. A mode control register (30) receives a mode control signal train via the serial input. Under the control of said mode control signal train the serial input and output can be shortcircuited to each other, or further registers (32, 34, 36) can be selectively filled and emptied. In this manner, both the interior of the integrated circuit and respective interconnection functions can easily be tested by a universal protocol. Integrated circuits and the carrier only require minor extension/adaptations.
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