LDPC decoder design to significantly increase throughput in ASIC by utilizing pseudo two port memory structure
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 1, 2019
Grant Date -
May 31, 2018
app pub date -
Nov 25, 2016
filing date -
Nov 25, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and apparatus allows single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the access table.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully