Method and structure for elevated source/drain with polished gate electrode insulated gate field effect transistors
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United States of America Patent
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Oct 31, 2000
Grant Date -
N/A
app pub date -
Dec 18, 1997
filing date -
Dec 18, 1997
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Abstract
A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.
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