Importance

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Abstract

The phase locked loop circuit according to the present invention is configured such that the CPU changes the time constant of the variable LPF filter to an optimum value in accordance with the state of the external signal fed from outside, for example by way of a selection switch activated in accordance with a control signal fed from the CPU, the responsive rate of the PLL circuit is raised, so that it can cope with jittery movements generated due to noise or a fluctuation of the supply voltage of the PLL circuit itself. On the other hand, in a case in which an external signal fed from outside the PLL circuit includes a considerable amount of noise or signal loss in itself, or suffers a signal loss, the CPU switches the time constant of the variable low-pass filter in accordance with the state of the external signal, and thereby sets the responsive rate of the PLL circuit to an optimum level, so that a fluctuation of the PLL circuit itself is suppressed, and the jittery movements of the OSD characters can thereby be eliminated.

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First Claim