Method and BIST architecture for fast memory testing in platform-based integrated circuit
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United States of America Patent
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May 8, 2007
Grant Date -
Jul 13, 2006
app pub date -
Nov 30, 2004
filing date -
Nov 30, 2004
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Abstract
The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
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