Method and system for at speed diagnostics and bit fail mapping
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United States of America Patent
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Sep 30, 2003
Grant Date -
N/A
app pub date -
Sep 26, 2000
filing date -
Sep 26, 2000
priority date (Note) -
Expired
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Abstract
This invention describes a method and apparatus, contained within an integrated circuit, for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST). A programmable clock counter, on the integrated circuit, stores a specified number of clock cycles and sends a signal to stop a BIST engine once the specified number of clock cycles have been generated. The intermediate results can then be mapped bit by bit in order to isolate the cause of failure.
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