Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device
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United States of America Patent
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Dec 1, 2009
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N/A
app pub date -
May 17, 2006
filing date -
Mar 1, 2006
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Abstract
A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).
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