Semiconductor memory storage device capable of high operating speed
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United States of America Patent
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May 30, 2006
Issued Date -
N/A
app pub date -
Dec 11, 2003
filing date -
Dec 18, 2002
priority date (Note) -
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Abstract
A semiconductor memory storage is disclosed, in which the gate of each of a plurality of n-channel transistors is connected to the corresponding one of a plurality of word lines on the output side of each word line driver. The source of the n-channel transistor is connected through a selective switching element to the gate of the corresponding one of a plurality of replica transistors connected to a dummy bit line. The gate of each replica transistor is connected to the corresponding one of discharge transistors. The dummy bit line is connected to a sense amplifier through a logic gate.
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