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Abstract

A random data generating apparatus which receives m bits, including: a first random data generator having: an m.times.2.sup.m decoder which receives the m bits and outputs n bits; registers arranged in series which shift and store the n bits, to generate shifted n bits; selection output circuits which receive the n bits from the m.times.2m decoder as selection signals, and provide a predetermined value with respect to valid bits among the n bits output from the m.times.2m decoder and provide the shifted n bits output from the registers with respect to invalid bits among the n bits output from the m.times.2.sup.m decoder, to generate selected n bits; and logic circuits which perform XOR operations on the selected n bits from the selection output circuits and respective ones of the shifted n bits output from the registers, and feed the results of the XOR operations back to a least significant one of the registers only in a case of valid bits among the n bits of output from the m.times.2.sup.m decoder. The registers generate the shifted n bits as random data.

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