Low power decompression of test cubes
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United States of America Patent
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Oct 25, 2011
Grant Date -
Dec 2, 2010
app pub date -
Aug 11, 2010
filing date -
Jul 21, 2006
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Abstract
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
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