Importance

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Abstract

An integrated circuit device comprising a memory cell array including a plurality of memory cells wherein each memory cell includes at least one electrically floating body transistor having source, drain and a body regions, wherein the body region is electrically floating and disposed between the source and drain regions; a gate is disposed over the body region. Each memory cell includes a first data state representative of a first charge in the body region and a second data state representative of a second charge in the body region. The integrated circuit device further includes operating characteristics adjustment circuitry, coupled to the memory cell array, to adjust one or more operating or response characteristics of one or more memory cells to improve the uniformity of operation/response characteristics of the memory cells of the memory cell array relative to the other memory cells of the array.

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First Claim