Hardware for supporting OS driven observation and anticipation based on more granular, variable sized observation units

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11366689
APP PUB NO 20200272512A1
SERIAL NO

16427910

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Abstract

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A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.

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Patent Owner(s)

  • NXP USA, INC.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brown, David Allen Austin, US 9 70
Ciusleanu, George Adrian Marasesti, RO 5 8
Mueller, Marcus Munich, DE 22 125
Rohleder, Michael Unterschleissheim, DE 41 210

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