Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition
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United States of America Patent
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Jul 17, 2007
Grant Date -
N/A
app pub date -
Apr 19, 2005
filing date -
Apr 19, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute processor boards distributed in an array of cabinets connected in series on each board and to respective routers in neighboring row cabinet boards with the routers in series connection coupled to routers in series connection in respective neighboring column cabinet boards. The array can include disconnect cabinets or respective routers in all boards in each cabinet connected in a toroid. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.
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