Hierarchical bus circuit having decoder generating local buses and devices select signals enabling switching elements to perform data transfer operations
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United States of America Patent
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Aug 24, 1993
Issued Date -
N/A
app pub date -
Nov 29, 1991
filing date -
Aug 18, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A bus circuit of a precharging type has an hierarchical structure comprising a higher rank bus and a plurality of lower rank buses connected in parallel thereto. A register block is connected to each of the lower rank buses, each register block comprising a plurality of registers connected in parallel to the lower rank bus. Both of the higher and the lower rank buses are precharged. The data of the register selected as a bus source is read onto the higher rank bus, thereby fluctuating a potential on the higher rank bus. Only the electric charges on the selected lower rank bus are discharged in response to the potential fluctuation and the selection signal. The total number of the registers coupled to the lower rank buses is the power of 2.
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