Packet processor memory interface with memory conflict valve checking
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United States of America Patent
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Oct 28, 2008
Grant Date -
N/A
app pub date -
Oct 31, 2007
filing date -
Oct 23, 2001
priority date (Note) -
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Abstract
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. When a potential memory conflict is detected, the values associated with the potentially conflicting memory operations are compared. In cases where the values match, no conflict is signaled. Such a value checking mechanism reduces the number of restarts needed in certain cases.
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