Layout verification method and device
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United States of America Patent
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Mar 4, 2008
Grant Date -
Mar 23, 2006
app pub date -
Sep 13, 2005
filing date -
Sep 17, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
There is provided a layout verification method including a space acquisition step of, with a wiring connected to a gate through a via as a target wiring, acquiring a space between the target wiring and a wiring adjacent thereto, a calculation step of calculating an antenna ratio according to the space between the target wiring and the adjacent wiring, the area of the gate, and the area of the target wiring, and an output step of outputting an antenna damage error when the antenna ratio exceeds a predetermined value.
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