Programmable error control circuit

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United States of America Patent

PATENT NO 6167026
SERIAL NO

09071431

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In a loop network system, a method and apparatus for automatic bypass of a node port associated with a hub port when the node port generates a number of errors beyond a threshold level. In one aspect, a programmable error control circuit provides this automatic bypass. The tolerance level is set through programmable parameters including a number of errors as well as a time interval to evaluate the number of errors detected. After a node port has been bypassed by the error control circuit, the error control circuit continues to monitor the error generation of the node port. When that error generation has reached an acceptable tolerance level, the error control circuit automatically reinserts the node port into the loop. The error control circuit provides statistical reporting on the number of errors as well as the number of bypasses generated at a particular hub port.

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Patent Owner(s)

  • AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brewer, David Anaheim, CA 13 236
Hashemi, Hossein Mission Viejo, CA 37 607
Henson, Karl M Rancho Santa Margarita, CA 18 288

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