Cache operations in a hybrid dual in-line memory module

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United States of America Patent

PATENT NO 11169920
SERIAL NO

16573305

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Abstract

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A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.

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Patent Owner(s)

  • MICRON TECHNOLOGY INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Anand, Gurpreet Pleasanton, US 24 207
Mittal, Samir Palo Alto, US 42 297
Ray, Anirban Santa Clara, US 30 204
Simionescu, Horia C Foster City, US 19 23
Stonelake, Paul San Jose, US 17 28
Walker, Robert M Raleigh, US 112 789

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