Memory device and method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11942185
APP PUB NO 20230162769A1
SERIAL NO

17832261

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Abstract

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An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time-to-digital convertor converts a time associated with the output voltage to a digital value.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Meng-Fan Taichung, TW 127 649
Hung, Je-Min Kaohsiung, TW 4 0
Khwa, Win-San Taipei, TW 55 33

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