Logic entity with two outputs for efficient adder and other macro implementations
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United States of America Patent
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Nov 10, 2009
Grant Date -
Mar 16, 2006
app pub date -
Aug 3, 2005
filing date -
Aug 3, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for a carry-in of one; a second lookup table for generating a first output for the carry out value for a carry-in of one and a second output for the sum value for a carry-in of zero; a first multiplexer is connected to a first input from the first output of the first lookup table and a second input from the first output of the second lookup table; a second multiplexer is connected to a first input from the second output of the first lookup table and a second input from the second output of the second lookup table; thereby, getting two output taps for sum and carry implementation.
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