Wafer having a dicing area having a step region covered with a conductive layer and method of manufacturing the same
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United States of America Patent
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-
Oct 30, 1990
Grant Date -
N/A
app pub date -
Jul 27, 1989
filing date -
Jul 27, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A conductive layer is formed at the step portion in a dicing line formed vertically and horizontally on a wafer and at a step portion of the region on which a test element for processing control formed inside of the dicing line or an alignment mark are formed, so as to completely cover the step portions. Since the conductive layer does not come off the step portions in subsequent steps, a short circuit of a wiring layer formed on a semiconductor chip region is prevented.
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