Recessed contact for multi-gate FET optimizing series resistance
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United States of America Patent
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Aug 27, 2013
Grant Date -
Jan 24, 2013
app pub date -
Sep 27, 2012
filing date -
Aug 28, 2009
priority date (Note) -
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Abstract
A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h1); forming a gate structure over the substrate, the gate structure having a length, a width and a height, the gate structure being perpendicular to the channel structure and being formed over the channel structure such that the channel structure passes through the width of the gate structure, where the height of the gate structure is greater than h1; reducing the height of the channel structure external to the gate structure so as to have a second height (h2); and depositing a silicide layer at least partially over the at least one channel structure external to the gate structure.
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