Circuit and method for testing a circuit having memory array and addressing and control unit
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United States of America Patent
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Mar 6, 2007
Grant Date -
Jan 13, 2005
app pub date -
Jul 12, 2004
filing date -
Jul 11, 2003
priority date (Note) -
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Abstract
A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.
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