Method of manufacturing flash memory device with reduced void generation

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United States of America Patent

PATENT NO 7892959
APP PUB NO 20090023278A1
SERIAL NO

12146183

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method of manufacturing a flash memory device that may include forming a first oxide film pattern and a first polysilicon pattern on a semiconductor substrate; sequentially forming a dielectric film pattern and a second polysilicon pattern on the semiconductor substrate including the first oxide film pattern and the first polysilicon pattern; forming a second oxide film pattern on the second polysilicon pattern; forming a gate by etching to the semiconductor substrate using the second oxide film pattern as a mask, the gate including the first oxide film pattern, the first polysilicon pattern, the dielectric film pattern and the second polysilicon pattern; removing the second oxide film pattern; forming a spacer on sidewalls of the gate; and forming an interlayer dielectric film on the semiconductor substrate including the gate and the spacer.

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Patent Owner(s)

  • DB HITEK CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kim, Sung-Jin Busan, KR 292 4650

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