Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit
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United States of America Patent
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May 31, 2011
Grant Date -
Apr 30, 2009
app pub date -
Oct 22, 2008
filing date -
Oct 29, 2007
priority date (Note) -
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Abstract
An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.
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