Apparatus and method for memory encryption with reduced decryption latency

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7472285
APP PUB NO 20050021986A1
SERIAL NO

10603680

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method and apparatus for memory encryption with reduced decryption latency. In one embodiment, the method includes reading an encrypted data block from memory. During reading of the encrypted data block, a keystream used to encrypt the data block is regenerated according to one or more stored criteria of the encrypted data block. Once the encrypted data block is read, the encrypted data block is decrypted using the regenerated keystream. Accordingly, in one embodiment, encryption of either random access memory (RAM) or disk memory is performed. A keystream is regenerated during data retrieval such that once the data is received, the data may be decrypted using a single clock operation. As a result, memory encryption is performed without exacerbating memory latency between the processor and memory.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Graunke, Gary L Hillsboro, OR 52 2603
Rozas, Carlos Portland, OR 37 602

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