Methods and apparatuses for external voltage test of input-output circuits
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United States of America Patent
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Dec 14, 2010
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app pub date -
Sep 12, 2006
filing date -
Sep 12, 2005
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Abstract
Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.
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