Programmable timing circuit for testing the cycle time of functional circuits on an integrated circuit chip
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United States of America Patent
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-
Jul 2, 2002
Grant Date -
Aug 9, 2001
app pub date -
Jan 24, 2001
filing date -
Jun 29, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A programmable timing circuit on an integrated circuit chip for testing the cycle time of functional circuits on the chip. The timing circuit includes a selectable input having at least two sources, one of which is a toggle circuit; a minimally delayed control path including a control latch; a programmable delay path in parallel with the control path and including a sample latch; and a comparator for comparing the state of the control latch and sample latches to provide a signal indicative of the delay path being longer than the control path. A plurality of configuration latches and multiplexers are provided for selecting the input source and routing an input signal through specific delay blocks to control the amount of delay in the delay path.
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