System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
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United States of America Patent
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Feb 2, 2010
Grant Date -
Sep 6, 2007
app pub date -
Apr 30, 2007
filing date -
Apr 2, 2004
priority date (Note) -
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Abstract
A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
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