Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches and control on the plate-lines of the bit-cell

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United States of America Patent

PATENT NO 11790972
SERIAL NO

17532652

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Abstract

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A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

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Patent Owner(s)

  • KEPLER COMPUTING INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dokania, Rajeev Kumar Beaverton, US 165 795
Manipatruni, Sasikanth Portland, US 347 2506
Mathuriya, Amrita Portland, US 186 947

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